8086/8088 HARDWARE SPECIFICATIONS
INTRODUCTION
In this chapter, the pin functions of both the 8086 and 8088 microprocessors are detailed and information is provided on the following hardware topics: clock generation, bus buffering, bus latching, timing, wait states, and minimum mode operation versus maximum mode operation. These simple microprocessors are explained first, because of their less intricate structures, as an introduction to the Intel microprocessor family.
Before it is possible to connect or interface anything to the microprocessor, it is necessary to understand the pin functions and timing. These rudimentary microprocessors contain the same basic pins as the latest Pentium 4 or Core2 microprocessor. Thus, the information in this chapter is essential to a complete understanding of memory and I/O interfacing, which we cover in the later chapters of the text.
CHAPTER OBJECTIVES
Upon completion of this chapter, you will be able to:
1. Describe the function of each 8086 and 8088 pin.
2. Understand the microprocessor’s DC characteristics and indicate its fan-out to common logic families.
3. Use the clock generator chip (8284A) to provide the clock for the microprocessor.
4. Connect buffers and latches to the buses.
5. Interpret the timing diagrams.
6. Describe wait states and connect the circuitry required to cause various numbers of waits.
7. Explain the difference between minimum and maximum mode operation.
PIN-OUTS AND THE PIN FUNCTIONS
In this section, we explain the function and (in certain instances) the multiple functions of each of the microprocessor’s pins. In addition, we discuss the DC characteristics to provide a basis for understanding the later sections on buffering and latching.
Figure 9–1 illustrates the pin-outs of the 8086 and 8088 microprocessors. As a close comparison reveals, there is virtually no difference between these two microprocessors—both are packaged in 40-pin dual in-line packages (DIPs).
As mentioned in Chapter 1, the 8086 is a 16-bit microprocessor with a 16-bit data bus and the 8088 is a 16-bit microprocessor with an 8-bit data bus. (As the pin-outs show, the 8086 has pin connections AD0–AD15, and the 8088 has pin connections AD0–AD7.) Data bus width there-fore the only major difference between these microprocessors. This allows the 8086 to transfer
16-bit data more efficiently.
There is, however, a minor difference in one of the control signals. The 8086 has an M>IO pin, and the 8088 has an IO/M pin. The only other hardware difference appears on Pin 34 of both integrated circuits: on the 8088, it is an SS0 pin, whereas on the 8086, it is a BHE /S7 pin.
Power Supply Requirements
Both the 8086 and 8088 microprocessors require +5.0 V with a supply voltage tolerance of ±10 percent. The 8086 uses a maximum supply current of 360 mA, and the 8088 draws a maximum of 340 mA. Both microprocessors operate in ambient temperatures of between 32° F and 180° F. This range is not wide enough to be used outdoors in the winter or even in the summer, but extended temperature-range versions of the 8086 and 8088 microprocessors are available. There is also a CMOS version, which requires a very low supply current and has an extended temperature range. The 80C88 and 80C86 are CMOS versions that require only 10 mA of power supply cur- rent and function in temperature extremes of -40° F through +225° F.
DC Characteristics
It is impossible to connect anything to the pins of the microprocessor without knowing the input current requirement for an input pin and the output current drive capability for an output pin. This knowledge allows the hardware designer to select the proper interface components for use with the microprocessor without the fear of damaging anything.
Input Characteristics. The input characteristics of these microprocessors are compatible with all the standard logic components available today. Table 9–1 depicts the input voltage levels and the input current requirements for any input pin on either microprocessor. The input current levels are very small because the inputs are the gate connections of MOSFETs and represent only leakage currents.
Output Characteristics. Table 9–2 illustrates the output characteristics of all the output pins of these microprocessors. The logic 1 voltage level of the 8086/8088 is compatible with that of most standard logic families, but the logic 0 level is not. Standard logic circuits have a maximum logic 0 voltage of 0.4 V, and the 8086/8088 has a maximum of 0.45 V. Thus, there is a difference of 0.05 V. This difference reduces the noise immunity from a standard level of 400 mV (0.8 V – 0.45 V)
to 350 mV. (The noise immunity is the difference between the logic 0 output voltage and the logic 0 input voltage levels.) The reduction in noise immunity may result in problems with long wire connections or too many loads. It is therefore recommended that no more than 10 loads of any type or combination be connected to an output pin without buffering. If this loading factor is exceeded, noise will begin to take its toll in timing problems.
Table 9–3 lists some of the more common logic families and the recommended fan-out from the 8086/8088. The best choice of component types for the connection to an 8086/8088 output pin is an LS, 74ALS, or 74HC logic component. Note that some of the fan-out currents calculate to more than 10 unit loads. It is therefore recommended that if a fan-out of more than 10 unit loads is required, the system should be buffered.
AD7–AD0 The 8088 address/data bus lines are the multiplexed address data bus of the 8088 and contain the rightmost 8 bits of the memory address or I/O port number whenever ALE is active (logic 1) or data whenever ALE is inactive (logic 0). These pins are at their high-impedance state during a hold acknowledge.
A15–A8 The 8088 address bus provides the upper-half memory address bits that are present throughout a bus cycle. These address connections go to their high- impedance state during a hold acknowledge.
AD15–AD8 The 8086 address/data bus lines compose the upper multiplexed address/data bus on the 8086. These lines contain address bits A15–A8 when- ever ALE is a logic 1, and data bus connections D15–D8 when ALE is a logic 0. These pins enter a high-impedance state when a hold acknowledge occurs.
A19/S6–A16/S3 The address/status bus bits are multiplexed to provide address signals A19–A16 and also status bits S6–S3. These pins also attain a high-impedance state during the hold acknowledge.
Status bit S6 is always a logic 0, bit S5 indicates the condition of the IF flag bit, and S4 and S3 show which segment is accessed during the current bus cycle. See Table 9–4 for the truth table of S4 and S3. These two status bits could be used to address four separate 1M byte memory banks by decoding them as A21 and A20.
RD Whenever the read signal is a logic 0, the data bus is receptive to data from the memory or I/O devices connected to the system. This pin floats to its high-impedance state during a hold acknowledge.
READY The READY input is controlled to insert wait states into the timing of the microprocessor. If the READY pin is placed at a logic 0 level, the micro- processor enters into wait states and remains idle. If the READY pin is placed at a logic 1 level, it has no effect on the operation of the microprocessor.
INTR Interrupt request is used to request a hardware interrupt. If INTR is held high when IF = 1, the 8086/8088 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.
TEST
The Test pin is an input that is tested by the WAIT instruction. If TEST is a logic 0, the WAIT instruction functions as an NOP and if TEST is a logic 1, the WAIT instruction waits for TEST to become a logic 0. The TEST pin is most often connected to the 8087 numeric coprocessor.
NMI The non-maskable interrupt input is similar to INTR except that the NMI interrupt does not check to see whether the IF flag bit is a logic 1. If NMI is activated, this interrupt input uses interrupt vector 2.
RESET The reset input causes the microprocessor to reset itself if this pin is held high for a minimum of four clocking periods. Whenever the 8086 or 8088 is reset, it begins executing instructions at memory location FFFFOH and dis- ables future interrupts by clearing the IF flag bit.
CLK The clock pin provides the basic timing signal to the microprocessor. The clock signal must have a duty cycle of 33 % (high for one third of the clocking period and low for two thirds) to provide proper internal timing for the 8086/8088.
VCC This power supply input provides a +5.0 V, ±10 % signal to the microprocessor.
GND The ground connection is the return for the power supply. Note that the 8086/8088 microprocessors have two pins labeled GND—both must be connected to ground for proper operation.
MN/MX
The minimum/maximum mode pin selects either minimum mode or maximum mode operation for the microprocessor. If minimum mode is selected, the MN/MX pin must be connected directly to +5.0 V.
BHE S7 The bus high enable pin is used in the 8086 to enable the most-significant data bus bits (D15–D8) during a read or a write operation. The state of S7 is always a logic 1.
Minimum Mode Pins. Minimum mode operation of the 8086/8088 is obtained by connecting the MN/MX pin directly to +5.0 V. Do not connect this pin to +5.0 V through a pull-up register, or it will not function correctly.
IO/M or M/ IO
WR
INTA
The IO/M (8088) or the M/ IO (8086) pin selects memory or I/O. This pin indicates that the microprocessor address bus contains either a memory address or an I/O port address. This pin is at its high-impedance state dur- ing a hold acknowledge.
The write line is a strobe that indicates that the 8086/8088 is outputting data to a memory or I/O device. During the time that the WR is a logic 0, the data bus contains valid data for memory or I/O. This pin floats to a high- impedance during a hold acknowledge.
The interrupt acknowledge signal is a response to the INTR input pin. The INTA pin is normally used to gate the interrupt vector number onto the data bus in response to an interrupt request.
ALE Address latch enable shows that the 8086/8088 address/data bus contains address information. This address can be a memory address or an I/O port number. Note that the ALE signal does not float during a hold acknowledge.
DT/ R
The data transmit/receive signal shows that the microprocessor data bus is transmitting (DT/R 1) or receiving (DT/R 0) data. This signal is used to enable external data bus buffers.
DEN Data bus enable activates external data bus buffers.
HOLD The hold input requests a direct memory access (DMA). If the HOLD sig- nal is a logic 1, the microprocessor stops executing software and places its address, data, and control bus at the high-impedance state. If the HOLD pin is a logic 0, the microprocessor executes software normally.
HLDA Hold acknowledge indicates that the 8086/8088 has entered the hold state.
SS0
The SS0 status line is equivalent to the S0 pin in maximum mode operation of the microprocessor. This signal is combined with IO/M and DT/R to decode the function of the current bus cycle (see Table 9–5).
Maximum Mode Pins. In order to achieve maximum mode for use with external coprocessors, connect the MN/MX pin to ground.
S2, S1, and S0
The status bits indicate the function of the current bus cycle. These signals are normally decoded by the 8288 bus controller described later in this chapter. Table 9–6 shows the function of these three status bits in the maximum mode.
RQ /GT1 and The request/grant pins request direct memory accesses (DMA) during RQ>GT0 maximum mode operation. These lines are bidirectional and are used to both request and grant a DMA operation.
LOCK
The lock output is used to lock peripherals off the system. This pin is activated by using the LOCK: prefix on any instruction.
QS1 and QS0 The queue status bits show the status of the internal instruction queue.
These pins are provided for access by the numeric coprocessor (8087). See Table 9–7 for the operation of the queue status bits.