Command Words of 8259A
The command words of 8259A are classified in two groups, viz.
initialization command words (ICWs) and operation command words (OCWs)Initialization Command Words (ICWs) Before it starts functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as initialization command words (ICWs). If A0 = 0 and D4 = 1, the control word is recognized as ICW1 It contains the control bits for edge/level triggered mode, sin- gle/cascade mode, call address interval and whether ICW4 is required or not, etc. If A0 = 1, the control word is recognized as ICW2. The ICW2 stores details regarding interrupt vector addresses. The initialisation sequence of 8259A is described in from of a flow chart in Fig. 1.3. The bit functions of the ICW1 and ICW2 are self explanatory as shown in Fig. 1.4.
Once ICW1 is loaded, the following initialization procedure is carried out internally.
(a) The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive.
(b) IMR is cleared.
(c) IR7 input is assigned the lowest priority.
(d) Slave mode address is set to 7.
(e) Special mask mode is cleared and status read is set to IRR.
(f) If IC4 = 0, all the functions of ICW4 are set to zero. Master/slave bit in ICW4 is used in the buffered mode only.
In an 8085 based system, A15 – A8 of the interrupt vector address are the respective bits of ICW2. In 8086/88 based system A15 – A11 of the interrupt vector address are inserted in place of T7 – T3 respectively and the remaining three bits (A8, A9 and A10) are selected depending upon the interrupt level, i.e. from 000 to 111 for IR0 to IR7.
ICW1 and ICW2 are compulsory command words in initialization sequence of 8259A as is evident from Fig. 1.3, while ICW3 and ICW4 are optional. The ICW3 is read only when there are more than one 8259As in the system, i.e. cascading is used (SNGL = 0). The SNGL bit in ICW1 indicates whether the 8259A is in cascade mode or not. The ICW3 loads an 8-bit slave register. Its detailed functions are as follows.
In master mode [i.e. SP = 1 or in buffer mode M/S = 1 in ICW4], the 8-bit slave register will be set bit-wise to ‘1’ for each slave in the system, as shown in Fig. 1.5. The requesting slave will then release the second byte of a CALL sequence.
In slave mode [i.e.SP=0 or if BUF=1 and M/S=0 in ICW4] bits D2 to D0 identify the slave, i.e 000 to 111 for slave 1 to slave 8. The slave compares the cascade inputs with these bits and if they are equal, the second byte if the CALL sequence is released by it on the data bus.
ICW4 The use of this command word depends on the IC4 bit of ICW1. If IC4 = 1, ICW4 is used, otherwise it is neglected. The bit functions of ICW4 are described as follows:
SFNM Special fully nested mode is selected, if SFNM = 1.
BUF If BUF = 1, the buffered mode is selected. In the buffered mode,
SP/EN acts as enable output and the master/slave is determined using the M/S bit of ICW4.
M/S If M/S = 1, 8259A is a master. If M/S = 0, 8259A is a slave. If BUF = 0, M/S is to be neglected.
AEOI If AEOI = 1, the automatic end of interrupt mode is selected.
µ PM If the µ PM bit is 0, the Mcs-85 system operation is selected and if/µ PM =1, 8086/88 operation is selected.
Fig1.6 shows the ICW4 bit positions
Operation Command Words
Once 8259A is initialized using the previously discussed command words for initialisation, it is ready for its normal function, i.e. for accepting the interrupts but 8259A has its own ways of handling the received interrupts called as modes of operation. These modes of operations can be selected by programming, i.e. writing three internal registers called as operation command word registers. The data written into them (bit pattern) is called as operation command words. In the three operation command words OCWl ,OCW2 and OCW3 every bit corresponds to some operational feature of the mode selected, except for a few bits those are either ‘1’ or ‘0’. The three operation command words are shown in Fig. 1.7 (a), (b) and (c) with the bit selection details. OCW1 is used to mask the unwanted interrupt requests. If the mask bit is ‘1’, the corresponding interrupt request is masked, and if it is ‘0’, the request is enabled. In OCW2 the three bits, viz. R, SL and EOI control the end of interrupt, the rotate mode and their combinations as shown in Fig. 1.7 (b), The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected for operation , if the SL bit is active, i.e. ‘1’. The details of OCW2 are shown in Fig. 1.7(b).
In operation command word 3 (OCW3), if the ESMM bit, i.e. enable special mask mode bit is set to ‘1’, the SMM bit is enabled to select or mask the special mask mode. When ESMM bit is ‘0’, the SMM bit is neglected. If the SMM bit, i.e. special mask mode bit is ‘1’, the 8259A will enter special mask mode provided ESMM = 1.
If ESMM = 1 and SMM = 0, the 8259A will return to the normal mask mode. The details of bits of OCW3 are given in Fig. 1.7 (c) along with their bit definitions.
Operating Modes of 8259
The different modes of operation of 8259A can be programmed by setting or resting the appropriate bits of the ICWs or OCWs as discussed previously. The different modes of opera· tion of 8259A are explained in the following text.
Fully Nested Mode This is the default mode of operation of 8259A. IR0 has the highest priority and IR7 has the lowest one. When interrupt requests are noticed, the highest priority request amongst them is determined and the vector is placed on the data bus. The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI command just before returning from the service routine or the AEOI bit is set. If the ISR (in service) bit is set, all the same or lower priority interrupts are inhibited but higher levels will generate an interrupt, that will be acknowledged only if the microprocessor’s interrupt enable flag (IF) is set. The priorities can afterwards be changed by programming the rotating priority modes.
End of Interrupt (EOI) The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command, issued before returning from the interrupt service routine. There are two types of EOI commands specific and non-specific. When 8259A is operated in the modes that preserve fully nested structure, it can determine which ISR bit is to be reset on EOT. When nonspecific EOI command is issued to 8259A it will automatically reset the highest ISR bit out of those already set.
When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to determine the last level acknowledged. In this case a specific EOI command is issued to reset a particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific EOI of 8259A, if it is in special mask mode.
Automatic Rotation This is used in the applications where all the interrupting devices are of equal priority. In this mode, an interrupt request (IR) level receives lowest priority after it is served while the next device to be served gets the highest priority in sequence. Once all the devices are served like this, the first device again receives highest priority.
Automatic EOI Mode Till AEOI = 1 in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of the last INTA pulse automatically. This mode should be used only when a nested multilevel interrupt structure is not required with a single 8259A.
Specific Rotation In this mode a bottom priority level can be selected, using L2, L1 and L0 in OCW2 and R =1, SL = 1, EOI = 0. The selected bottom priority fixes other priorities. If IR5 is selected as a bottom priority, then IR5 will have least priority and IR4 will have a next higher priority. Thus IR6 will have the highest priority. These priorities can be changed during an EOI command by programming the rotate on specific EOI command in OCW2
Special Mask Mode In special mask mode, when a mask bit is set in OCWl, it inhibits further interrupts at that level and enables interrupt from other levels, which are not masked.
Edge and Level Triggered Mode This mode decides whether the interrupt should be edge triggered or level triggered. If bit LTIM of ICWl = 0, they are edge triggered, otherwise the interrupts are level triggered.
Reading 8259 Status The status of the internal registers of 8259A can be read using this mode. The OCW3 is used to read IRR and ISR while OCWl is used to read IMR. Reading is possible only in no polled mode.
Poll Command In polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by not connecting INT output or by masking INT input of the microprocessor. The poll mode is entered by setting P = 1 in OCW3. The 8259A is polled by using software execution by microprocessor instead of the requests on INT input. The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a request. The priority level is read and a data word is placed on to data bus, after RD is activated. The data word is shown in Fig. 1.8.
Fig. 1.8. Data Word of 8259
A poll command may give you more than 64 priority levels. Note that this has nothing to do with the 8086 interrupt structure and the interrupt priorities.
Special Fully Nested Mode This mode is used in more complicated systems, where cascading is used and the priority has to be programmed in the master using ICW4. This is somewhat similar to the normal nested mode. In this mode, when an interrupt request from a certain lave is in service, this slave can further send requests to the master, if the requesting device connected to the slave has higher priority than the one being currently served. In this mode, the master interrupts the CPU only when the interrupting device has a higher or the same priority than the one currently being served. In normal mode, other requests than the one being served are masked out.
When entering the interrupt service routine the software has to check whether this is the only request from the slave. This is done by sending a non- specific EOI command to the slave and then reading its ISR and checking for zero. If its zero, a non-specific EOI can be sent to the master, otherwise no EOI should be sent. This mode is important, since in the absence of this mode, the slave would interrupt the master only once and hence the priorities of the ‘lave inputs would have been disturbed.
Buffered Mode When the 8259A is used in the systems where bus driving buffers are used on data buses (e.g. cascade systems). The problem of enabling the buffers exists. The 8259A sends buffer enable signal on SP /EN pin, whenever data is placed on the bus.
Cascade Mode The 8259A can be connected in a system containing one master and eight laves (maximum) to handle up to 64 priority levels. The master controls the slaves using CAS0-CAS2 which act as chip select inputs (encoded) for slaves. In this mode, the slave INT outputs are connected with master IR inputs. When a slave request line is activated and acknowledged, the master will enable the slave to release the vector address during second pulse of INTA sequence. The cascade lines are normally low and contain slave address codes from the trailing edge of the first INT A pulse to the trailing edge of the second INT A pulse. Each 8259A in the system must be separately initialized and programmed to work in different modes. The EOI command must be issued twice, one for master and the other for the slave. A separate address decoder is used to activate the chip select line of each 8259A.
Interfacing and programming 8259
Example:
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP to initialize the 8259A in single level triggered mode. Then set the 8259A to operate with IR6 masked, IR4 as bottom priority level, with special EOI mode. Set special mask mode of 8259A. Read IRR and ISR into registers BH and BL respectively.
Solution:
Let the starting address is 0000:0010. The interconnections of 8259A with 8086 are as shown in Fig 1.10. The 8259 is interfaced with lower byte of the 8086 data bus, hence A0 line of the microprocessor system is abondened and A1 of the microprocessor system is connected with A0 of the 8259A. Before going for an ALP, all the initialisation command words (ICWS) and Operation command word (OCWS) must be decided. ICW1 decides single level triggered, address interval of 4 as given below.
Assembly language program
CODE SEGMENT
ASSUME CS:CODE
START: MOV AL,1FH ; Set the 8259A in single, level
MOV DX,0740H
OUT DX,AL ;triggered mode with call
MOV DX,0742H ;address of interval of 4
MOV AL,83H ;Select vector address 0010H
OUT DX,AL ;for IR3(ICW2)
MOV AL,01H :ICW4 for 8086 system, normal
OUT DX,AL ; EOI, non-buffered, SFNM masked
MOV AL,40H
OUT DX,AL ;OCW1 for IR6 masked
MOV AL,E4H ;Specific EOI with rotating
MOV DX,0740H
OUT DX,AL ; Priority and bottom level of
MOV AL,6AH ;IR4 with OCW2 Write OCW3 reading
OUT DX,AL ; IRR and store in BH
IN AL,DX
MOV BH,AL
MOV AL,6BH ; Write OCW3 to read
OUT DX,AL ; ISR and store in BL
IN AL,DX
MOV BL,AL
MOV AH,4CH ; Return to DOS
INT 21H
CODE ENDS
END START