Module 3 learning unit 9:
PIO 8255
• The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8- bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines.
• The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port C upper.
• The port A lines are identified by symbols PA0-PA7 while the port C lines are identified as PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can be used in combination as an 8-bit port C.
• Both the port C are assigned the same address. Thus one may have either three 8- bit I/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can
function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register (CWR).
• The internal block diagram and the pin configuration of 8255 are shown in fig.
• The 8-bit data bus buffer is controlled by the read/write control logic. The read/write control logic manages all of the internal and external transfers of both data and control words.
• RD , WR , A1, A0 and RESET are the inputs provided by the microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used to interface the 8255 internal data bus with the external system data bus.
• This buffer receives or transmits data upon the execution of input or output instructions by the microprocessor. The control words or status information is also transferred through the buffer.
• The signal description of 8255 are briefly presented as follows :
• PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines depending upon the control word loaded into the control word register.
• PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines.
• This port also can be used for generation of handshake lines in mode 1 or mode 2.
• PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.
• PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in the same way as port A.
• RD : This is the input line driven by the microprocessor and should be low to indicate read operation to 8255.
• WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.
• CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals, otherwise RD and WR signal are neglected.
• A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD , WR and CS from the following operations for 8255. These address lines are used for addressing any one of the four registers, i.e. three ports and a control word register as given in table below.
• In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.
• D0-D7 : These are the data bus lines those carry data or control word to/from the microprocessor.
• RESET : A logic high on this line clears the control word register of 8255. All ports are set as input ports by default after reset.
Control Word Register
Block Diagram of 8255 (Architecture)
• It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C
• Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 to system databus. Data is transmitted or received by the buffer on execution of input or output instruction by the CPU.
• Control word and status information are also transferred through this unit.
• Read/Write control logic: This unit accepts control signals ( RD , WR ) and also inputs from address bus and issues commands to individual group of control blocks (Group A, Group B).
• It has the following pins.
a) CS – Chipselect : A low on this PIN enables the communication between CPU and 8255.
b) RD (Read) – A low on this pin enables the CPU to read the data in the ports or the status word through data bus buffer.
c) WR (Write) : A low on this pin, the CPU can write data on to the ports or on to the control register through the data bus buffer.
d) RESET: A high on this pin clears the control register and all ports are set to the input mode
e) A0 and A1 (Address pins): These pins in conjunction with RD and WR pins control the selection of one of the 3 ports.
• Group A and Group B controls : These block receive control from the CPU and issues commands to their respective ports.
• Group A – PA and PCU (PC7 –PC4)
• Group B – PCL (PC3 – PC0)
• Control word register can only be written into no read operation of the CW register is allowed.
• a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be programmed in 3 modes – mode 0, mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer. This port can be divided into two 4 bit ports and can be used as control signals for port A and port B. it can be programmed in mode 0.
Modes of Operation of 8255
• These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.
• Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different types of applications, mode 0, mode 1 and mode 2.
• BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table.
• I/O Modes :
a) Mode 0 (Basic I/O mode): This mode is also called as basic input/output mode. This mode provides simple input and output capabilities using each of the three ports. Data can be simply read from and written to the input and output ports respectively, after appropriate initialisation.
Mode 0
• The salient features of this mode are as listed below:
1. Two 8-bit ports (port A and port B)and two 4-bit ports (port C upper and lower) are available. The two 4-bit ports can be combinedly used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configuration are possible.
• All these modes can be selected by programming a register internal to 8255 known as CWR.
• The control word register has two formats. The first format is valid for I/O modes of operation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit set/reset (BSR) mode of operation. These formats are shown in following fig.
Control Word Format of 8255
b) Mode 1: (Strobed input/output mode) In this mode the handshaking control the input and output action of the specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for port A.
This group including port A and PC3-PC5 from group A. Thus port C is utilized for generating handshake signals. The salient features of mode 1 are listed as follows:
1. Two groups – group A and group B are available for strobed data transfer.
2. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
3. The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched.
4. Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are used to generate control signals for port A. the lines PC6, PC7 may be used as independent data lines.
• The control signals for both the groups in input and output modes are explained as follows:
Input control signal definitions (mode 1):
• STB (Strobe input) – If this lines falls to logic low level, the data available at 8-bit input port is loaded into input latches.
• IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data has been loaded into latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising edge of RD input.
• INTR (Interrupt request) – This active high output signal can be used to interrupt the CPU whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF pin. INTE is an internal flag that can be controlled by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig.
• INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of the processor by putting the data on the bus and sending the strobe signal.
Output control signal definitions (mode 1) :
• OBF (Output buffer full) – This status signal, whenever falls to low, indicates that CPU has written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR signal and reset by a low going edge at the ACK input.
• ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given by an output device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port is received by the output device.
• INTR (Interrupt request) – Thus an output signal that can be used to interrupt the CPU when an output device acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2 respectively.
Mode 1 Control Word Group A Mode 1 Control Word Group B
• Mode 2 (Strobed bidirectional I/O): This mode of operation of 8255 is also called as strobed bidirectional I/O. This mode of operation provides 8255 with an additional features for communicating with a peripheral device on an 8-bit data bus. Handshaking signals are provided to maintain proper data flow and synchronization between the data transmitter and receiver. The interrupt generation and other functions are similar to mode 1.
• In this mode, 8255 is a bidirectional 8-bit port with handshake signals. The Rd and WR signals decide whether the 8255 is going to operate as an input port or output port.
• The Salient features of Mode 2 of 8255 are listed as follows:
1. The single 8-bit port in group A is available.
2. The 8-bit port is bidirectional and additionally a 5-bit control port is available.
3. Three I/O lines are available at port C.(PC2 – PC0)
4. Inputs and outputs are both latched.
5. The 5-bit control port C (PC3-PC7) is used for generating / accepting handshake signals for the 8-bit data transfer on port A.
• Control signal definitions in mode 2:
• INTR – (Interrupt request) As in mode 1, this control signal is active high and is used to interrupt the microprocessor to ask for transfer of the next data byte to/from it. This signal is used for input (read) as well as output (write) operations.
• Control Signals for Output operations:
• OBF (Output buffer full) – This signal, when falls to low level, indicates that the CPU has written data to port A.
• ACK (Acknowledge) This control input, when falls to logic low level, acknowledges that the previous data byte is received by the destination and next byte may be sent by the processor. This signal enables the internal tristate buffers to send the next data byte on port A.
• INTE1 (A flag associated with OBF) This can be controlled by bit set/reset mode with PC6.
• Control signals for input operations :
• STB (Strobe input) A low on this line is used to strobe in the data into the input latches of 8255.
• IBF (Input buffer full) When the data is loaded into input buffer, this signal rises
to logic ‘1’. This can be used as an acknowledge that the data has been received by the receiver.
• The waveforms in fig show the operation in Mode 2 for output as well as input port.
• Note: WR must occur before ACK and STB must be activated before RD .
Mode 2 Bidirectional Data Transfer
• The following fig shows a schematic diagram containing an 8-bit bidirectional port, 5-bit control port and the relation of INTR with the control pins. Port B can either be set to Mode 0 or 1 with port A(Group A) is in Mode 2.
• Mode 2 is not available for port B. The following fig shows the control word.
• The INTR goes high only if either IBF, INTE2, STB and RD go high or OBF, INTE1, ACK and WR go high. The port C can be read to know the status of the peripheral device, in terms of the control signals, using the normal I/O instructions.
• Compatible with All Intel and Most other Microprocessors
• Handles Inputs from DC to 10 MHz
• 8 MHz 8254
• 10 MHz 8254-2
• Status Read-Back Command
• Six Programmable Counter Modes
• Three Independent 16-Bit Counters
• Binary or BCD Counting
• Single a 5V Supply
• Standard Temperature Range
• The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design.
• It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz.
• All modes are software programmable. The 8254 is a superset of the 8253.The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.
Figure 1. Pin Configuration
Figure 2. 8254 Block
Functional Description
• The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems.
• It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software.
• The 8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay.
• After the desired delay, the 8254 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated.
• Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are:
• Real time clock
• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Block Diagram
• DATA BUS BUFFER: This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus, see the figure : Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions.
• READ/WRITE LOGIC : The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1 and A0 select one of the three counters or the Control Word Register to be read from/written into.
• A “low” on the RD input tells the 8254 that the CPU is reading one of the counters.
Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions
• A “low” on the WR input tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 8254 has been selected by holding CS low.
• CONTROL WORD REGISTER :The Control Word Register (see Figure 4) is selected by the Read/Write Logic when A1,A0 = 11. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.
Figure 4. Block Diagram Showing Control Word Register and Counter Functions
• The Control Word Register can only be written to; status information is available with the Read-Back Command.
• COUNTER 0, COUNTER 1, COUNTER 2 :These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a single counter is shown in Figure 5.
• The Counters are fully independent. Each Counter may operate in a different Mode.
• The Control Word Register is shown in the figure, it is not part of the Counter itself, but its contents determine how the Counter operates.
• The status register, shown in Figure 5, when latched, contains the current contents of the Control Word Register and status of the output and null count flag. (See detailed explanation of the Read-Back command.)
• The actual counter is labelled CE (for “Counting Element”). It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for “Output Latch”; the subscripts M and L stand for “Most significant byte” and “Least significant byte’‘respectively.
Figure 5. Internal Block Diagram of a Counter
• Both are normally referred to as one unit and called just OL. These latches normally “follow’‘ the CE, but if a suitable Counter Latch Command is sent to the 8254, the latches “latch” the present count until read by the CPU and then return to “following” the CE.
• One latch at a time is enabled by the counter’s Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read; whenever you read the count, it is the OL that is being read.
• Similarly, there are two 8-bit registers called CRM and CRL (for “Count Register”). Both are normally referred to as one unit and called just CR.
• When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously.
• CRM and CRL are cleared when the Counter is programmed. In this way, if the Counter has been programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero.
• Note that the CE cannot be written into, whenever a count is written, it is written into the CR.
• The Control Logic is also shown in the diagram.
• CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic.
• 8254 SYSTEM INTERFACE: The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner as all other peripherals of the family.
• It is treated by the system’s software as an array of peripheral I/O ports; three are counters and the fourth is a control register for MODE programming.
• Basically, the select inputs A0,A1 connect to the A0,A1 address bus signals of the CPU. The CS can be derived directly from the address bus using a linear select method. Or it can be connected to the output of a decoder, such as an Intel 8205 for larger systems.
• Programming the 8254: Counters are programmed by writing a Control Word and then an initial count.
• The Control Words are written into the Control Word Register, which is selected when A1,A0 = 11. The Control Word itself specifies which Counter is being programmed.
Figure 6. 8254 System Interface
• Control Word Format: A1,A0 = 11, CS = 0, RD = 1, WR = 0.
• By contrast, initial counts are written into the Counters, not the Control Word Register. The A1,A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used.
• Write Operations: The programming procedure for the 8254 is very flexible.
Only two conventions need to be remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).
• Since the Control Word Register and the three Counters have separate addresses (selected by the A1,A0 inputs), and each Control Word specifies the Counter it applies to (SC0,SC1 bits), no special instruction sequence is required.
• Any programming sequence that follows the conventions in Figure 7 is acceptable.
NOTE: Don’t care bits (X) should be 0 to insure compatibility with future Intel products.
Figure 7. Control Word Format
• A new initial count may be written to a Counter at any time without affecting the Counter’s programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format.
• If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect count.
Figure 8. A Few Possible Programming Sequences
• Read Operations: It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 8254.
• There are three possible methods for reading the counters: a simple read operation, the Counter Latch Command, and the Read-Back Command.
• Each is explained below. The first method is to perform a simple read operation.
To read the Counter, which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.
• Otherwise, the count may be in the process of changing when it is read, giving an undefined result.
• COUNTER LATCH COMMAND: The second method uses the “Counter Latch Command”.
• Like a Control Word, this command is written to the Control Word Register, which is selected when A1,A0 = 11. Also like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word.
• The selected Counter’s output latch (OL) latches the count at the time the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed).
Figure 9. Counter Latching Command Format
• The count is then unlatched automatically and the OL returns to “following” the counting element (CE).
• This allows reading the contents of the Counters “on the fly” without affecting counting in progress.
• Multiple Counter Latch Commands may be used to latch more than one Counter.
Each latched Counter’s OL holds its count until it is read.
• Counter Latch Commands do not affect the programmed Mode of the Counter in any way.
• If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued.
• With either method, the count must be read according to the programmed format; specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other, read or write or programming operations of other Counters may be inserted between them.
• Another feature of the 8254 is that reads and writes of the same Counter may be interleaved.
• Example: If the Counter is programmed for two byte counts, the following sequence is valid.
1) Read least significant byte.
2) Write new least significant byte.
3) Read most significant byte.
4) Write new most significant byte.
• If a Counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read.
• READ-BACK COMMAND: The third method uses the Read-Back Command.
This command allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter (s).
• The command is written into the Control Word Register and has the format shown in Figure 10. The command applies to the counters selected by setting their corresponding bits D3, D2, D1 = 1.
• The read-back command may be used to latch multiple counter output latches
(OL) by setting the COUNT bit D5 = 0 and selecting the desired counter (s). This single command is functionally equivalent to several counter latch commands, one for each counter latched.
• Each counter’s latched count is held until it is read (or the counter is reprogrammed).
• The counter is automatically unlatched when read, but other counters remain latched until they are read. If multiple count read-back commands are issued to the same counter without reading the count, all but the first are ignored; i.e., the count which will be read is the count at the time the first read-back command was issued.
• The read-back command may also be used to latch status information of selected counter (s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a counter is accessed by a read from that counter.
• The counter status format is shown in Figure 11.
• Bits D5 through D0 contain the counter’s programmed Mode exactly as written in the last Mode Control Word. OUTPUT bit D7 contains the current state of the OUT pin.
• This allows the user to monitor the counter’s output via software, possibly eliminating some hardware from a system. NULL COUNT bit D6 indicates when the last count written to the counter register (CR) has been loaded into the counting element (CE).
• The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions, but until the count is loaded into the counting element (CE), it can’t be read from the counter.
Figure 11. Status Byte
• If the count is latched or read before this time, the count value will not reflect the new count just written. The operation of Null Count is shown in Figure 12.
• If multiple status latch operations of the counter (s) are performed without reading the status, all but the first are ignored; i.e., the status that will be read is the status of the counter at the time the first status read-back command was issued.
• Both count and status of the selected counter (s) may be latched simultaneously by setting both COUNT and STATUS bits D5,D4 = 0. This is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also.
Figure 12. Null Count Operation
• Specifically, if multiple count and/or status read-back commands are issued to the same counter (s) without any intervening reads, all but the first are ignored. This is illustrated in Figure 13.
• If both count and status of a counter are latched, the first read operation of that counter will return latched status, regardless of which was latched first. The next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. Subsequent reads return unlatched count.
Figure 13. Read-Back Command Example
Figure 14. Read/Write Operations Summary
• Mode Definitions :The following are defined for use in describing the operation of the 8254.
• CLK Pulse: A rising edge, then a falling edge, in that order, of a Counter’s CLK input.
• Trigger: A rising edge of a Counter’s GATE input.
• Counter loading: The transfer of a count from the CR to the CE (refer to the “Functional Description”).
• MODE 0: INTERRUPT ON TERMINAL COUNT :
• Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero.
• OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter.
• GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT.
• After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not go high until N a 1 CLK pulses after the initial count is written.
• If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens:
1) Writing the first byte disables counting. OUT is set low immediately (no clock pulse required).
2) Writing the second byte allows the new count to be loaded on the next CLK pulse.
• This allows the counting sequence to be synchronized by software. Again, OUT does not go high until Na1 CLK pulses after the new count of N is written.
• If an initial count is written while GATE e 0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT will go high N CLK pulses later; no CLK pulse is needed to load the Counter as this has already been done.
Figure 15. Mode 0
Note:
1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.
2. The counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a control word of 10 HEX is written to the counter.
4. LSB stands for “Least Significant Byte” of count.
5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is the most significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be
read. N stands for an undefined count. Vertical lines show transitions between count values.
• MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT: OUT will be initially high.
• OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero.
• OUT will then go high and remain high until the CLK pulse after the next trigger.
• After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
• The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT.
• If a new count is written to the Counter during a oneshot pulse, the current one- shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
Figure 16. Mode 1
• MODE 2: RATE GENERATOR: This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt.
• OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated.
• Mode 2 is periodic, the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles.
• GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low during an output pulse, OUT is set high immediately.
• A trigger reloads the Counter with the initial count on the next CLK pulse, OUT goes low N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Counter.
• After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT goes low N CLK Pulses after the initial count is written.
• This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence.
• If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count.
• Otherwise, the new count will be loaded at the end of the current counting cycle.
In mode 2, a COUNT of 1 is illegal.
• MODE 3: SQUARE WAVE MODE :Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high.
Figure 17. Mode 2
• When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely.
• An initial count of N results in a square wave with a period of N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high immediately; no CLK pulse is required.
• A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter.
• After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also.
• Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise, the new count will be loaded at the end of the current half-cycle.
• Mode 3:Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses.
• When the count expires OUT changes value and the Counter is reloaded with the initial count. The above process is repeated indefinitely.
• Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses.
Figure 18. Mode 3
• One CLK pulse after the count expires, OUT goes low and the Counter is reloaded with the initial count minus one.
• Succeeding CLK pulses decrement the count by two.
• When the count expires, OUT goes high again and the Counter is reloaded with the initial count minus one. The above process is repeated indefinitely.
• So for odd counts, OUT will be high for (N – 1)/2 counts and low for (N – 1)/2 counts.