Direct Addressing Mode
All 128 bytes of internal RAM and the SFRs may be addressed directly using the single byte address assigned to each RAM location and each special-function register.
Internal RAM uses addresses from 00 to 7Fh to address each byte. The SFR addresses exist from 80h to FFh at the following locations:
|
SFR |
ADDRESS (HEX) OED |
|
A |
0E0 |
|
B |
0F0 |
|
DPL |
82 |
|
DPH |
83 |
|
IE |
0A8 |
|
IP |
0B8 |
|
PO |
80 |
|
Pl |
90 |
|
P2 |
DAD |
|
P3 |
080 |
|
PCON |
87 |
|
PSW |
0DD |
|
SBUF |
99 |
|
SCON |
98 |
|
SP |
81 |
|
TCON |
88 |
|
TMOD |
89 |
|
TH0 |
8C |
|
TL0 |
8A |
|
TH1 |
8D |
|
TLl |
8B |
Note the use of a leading 0 for all numbers that begin with an alphabetic (alpha) character.
RAM addresses 00 to 1Fh are also the locations assigned to the four banks of eight working registers, R0 to R7. This assignment means that R2 of register bank 0 can be
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addressed in the registermodeasR2orinthedirectmodeas02h.The direct addresses of |
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the working registers are as follows: |
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|
BANK REGISTER |
ADDRESS (HEX) |
BANK REGISTER |
ADDRESS (HEX) |
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|
0 |
R0 |
00 |
2 |
R0 |
10 |
|
|
0 |
R1 |
01 |
2 |
R1 |
11 |
|
|
0 |
R2 |
02 |
2 |
R2 |
12 |
|
|
0 |
R3 |
03 |
2 |
R3 |
13 |
|
|
0 |
R4 |
04 |
2 |
R4 |
14 |
|
|
0 |
R5 |
05 |
2 |
R5 |
15 |
|
|
0 |
R6 |
06 |
2 |
R6 |
16 |
|
|
0 |
R7 |
07 |
2 |
R7 |
17 |
|
|
1 |
R0 |
08 |
3 |
R0 |
18 |
|
|
1 |
R1 |
09 |
3 |
R1 |
19 |
|
|
1 |
R2 |
0A |
3 |
R2 |
1A |
|
|
1 |
R3 |
0B |
3 |
R3 |
1B |
|
|
1 |
R4 |
0C |
3 |
R4 |
1C |
|
|
1 |
R5 |
0D |
3 |
R5 |
1D |
|
|
1 |
R6 |
0E |
3 |
R6 |
1E |
|
|
1 |
R7 |
0F |
3 |
R7 |
1F |
Only one bank of working registers is active at any given time. The PSW special function register holds the bank-select bits, RSO and RS 1, which determine which register bank is in use.
When the 8051 is reset, RS0 and RS 1 are set to 00b to select the working registers in bank 0, located from 00h to 07h in internal RAM. Reset also sets SP to 07h, and the stack will grow up as it is used. This growing stack will overwrite the register banks above bank 0. Be sure to set the SP to a number above those of any working registers the program may use.
The programmer may choose any other bank by setting RS0 and RS 1 as desired; this bank change is often done to "save" one bank and choose another when servicing an interrupt or using a subroutine.
The moves made possible using direct, immediate, and register addressing modes are as follows:
|
Mnemonic |
Operation |
|
MOV A, add |
Copy data from direct address add to register A |
|
MOV add ,A |
Copy data from register A to direct address add |
|
MOV Rr, add |
Copy data from direct address add to register Rr |
|
MOV add, Rr |
Copy data from register Rr to direct address add |
|
MOV add, #n |
Copy immediate data byte n to direct address add |
|
MOV add I ,add2 |
Copy data from direct address add2 to direct address add1 |
The following table shows examples of MOV opcodes using direct, immediate, and register addressing modes:
|
Mnemonic |
Operation |
|
|
MOV A,80h |
Copy data from the port 0 pins to register A |
|
|
MOV 80h,A |
Copy data from register A to the port 0 latch |
|
|
MOV 3Ah,#3Ah |
Copy immediate data byte 3Ah to RAM location 3Ah |
|
|
MOV RO,12h |
Copy data from RAM location 12h to register RO |
|
|
MOY 8Ch,R7 |
Copy data from register R 7 to timer 0 high byte |
|
|
MOY 5Ch,A |
Copy data from register A to RAM location 5Ch |
|
|
MOY OA8h,77h |
Copy data from RAM location 77h to IE register |
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CAUTION
MOV instructions that refer to direct addresses above 7Fh that are not SFRs will result in errors. The SFRs are physically on the chip; all other addresses above 7Fh do not physically exist.
Moving data to a port changes the port latch; moving data from a port gets data from the port pins.
Moving data from a direct address to itself is not predictable and could lead to errors.