Design of a single-state Audio-frequency Amplifer

Design of a single-state Audio-frequency Amplifer

In the design of a single-stage audio-frequency amplifier a number of factors must be taken into account. These include the choice of operating point and the required voltage gain. Other factors such as the required bandwidth and the noise performance are also of importance but are beyond the scope of this book. There are several different approaches to the design of an amplifier available and here just one of them is given.

Suppose that an amplifier stage is to deliver the maximum possible output voltage so that the d.c. collector-emitter voltage V_CE will be set at one-half of the supply voltage V_CC. Assuming for the moment, that the rest of the supply voltage is dropped across the collector

resistor R₃, then V_cc/2 = l_cR₃). This gives the maximum possible output voltage. The voltage gain Av = g_mR₃ = 40l_c X V_cc/2l_c = 20 V_cc . This approximate relationship will allow a choice to be made of the collector supply voltage to allow a wanted gain to be obtained, or alternatively, if the supply voltage is already fixed by other considerations, it will establish the maximum possible voltage gain.

A suitable d.c. load line can be drawn on the output characteristics of the transistor and the operating point located at V_cc/2 volts. This allows the collector current to be detennined. Alternatively, a collector current may be arbitrarily selected, which will very often be the value quoted in the data sheet for the typical value of h_FE.

The collector resistor can then be determined from R₃ = V_cc/2I_c. The potential divider bias circuit must establish the required operat­ing point and also provide adequate d.c. stability. If h_FER₄ >> R₁R₂/(R₁ + R₂) the collector current will be very nearly equal to (V_B – V_BE)IR₄, i.e. it will be independent of h_FE. The collector current is then still subject to variations due to changes in V_SE but this factor may be minimized by making V_B several times larger than V_BE Since V_E = V_E + V_BE this means that the voltage across R₄ should not be less than about 1V. A good rule is to make V_E equal to V_cc/10 with a minimum value of I V.

For the circuit to operate correctly the base voltage V_B should remain more or less constant at V_B = VccR₂/(R₁ + R₂) as the collector current and thus V_E = I_cR₄ varies. To achieve this the current flowing through the lower bias resistor R₂ must be several times larger, by a factor n, than the base current I_B = Ic/h_FE . The larger the factor n the better will be the d.c. stability of the circuit but the lower will be the values of the resistors R₁ and R₂. Since R1 and R2 are effectively in parallel, both with the signal path and with one another, their values must not be too small. This means that the choice of n must be a compromise between the a.c. and d.c. performances of the circuit. A suitable choice for n is 10.

Then, R₂ = V_B/nI_B and R₁ = (Vcc – V_B)/(n+ I)I_B. Calculation of suitable values for the coupling and decoupling capacitors is more difficult and values such as those quoted in Table 1 should be used.

Example 14

Design an audio-frequency single-stage amplifier to have a voltage gain of about 240 using the transistor whose characteristics are given in Fig. 36. The maximum possible output voltage is required.

Solution

Voltage gain = 240 = 20V_cc , or V_cc = 240/20 = 12 V. The operating point is then set at V_CE = 6 V, I_B = 15 /πA . The d.c. load line has been drawn through these two points. The d.c. collector current is then 1.5 mA and h_FE = (1.5 x 10^-3)/(15 x 10^-6) = 100.

The slope of the load line is (12 – 6)/(1.5 – 0) x 10^-3 = 4000 Ω. The emitter voltage V_E = Vcc/l0 = 12/10 = 1.2 V. Hence, R₄ = 1.2/(1.5 X

10^-3) = 800 Ω. Choosing the nearest preferred values for R₃ and R₄; R₃ = 3900 Ω and OO R₄ = 820 Ω. Now the voltage drop across (R₃ + R₄) is 1.5 X 10^-3 X (3900 + 820) = 7 V which leaves V_CE. as 5 V.

The base current I_B = I_c/h_FE = 15 πA. Therefore, choose the current in R₂ to be 150 μA. From Fig. 36a , when I_B = 15 μA, V_BE = 0.65 V, giving Vs = 1.2 + 0.65 = 1.85 V. Then,

R₂ = 1.85/(10 x 15 x 10^-6) = 12.3 kΩ

R₁ = (12 – 1.85)/(11 x 15 x 10^-6) = 61.5 kΩ

Choosing the nearest preferred values, R₂ = 12 kΩ and R₁ = 62 kΩ.

The midband voltage gain will be g_mR₃ = 38 x 1.5 x 10^-3 x 3900 = 222. To increase the gain nearer to the wanted target of 240 the next higher preferred value for R₃ could be used. i.e. R₃ = 4300 Ω . Then A_v = 245 but the maximum output voltage will be reduced .